Because of their capacity of high input-output (IO) number and high speed, ball grid array (BGA) packages have become the main stream of package types for advanced integrated circuit (IC) products. Such advanced IC products produce lots of heat which require the use of heat spreaders to form heat spreader ball grid array (HSBGA) packages in order to dissipate the extra heat. However, such HSBGA packages have higher thermal stresses while TC/TS tests and low dielectric constant (k) (LK) materials show weak robustness with the HSBGA packages cracking or delaminating, thus failing qualification tests. LK (low-k) is a dielectric material having a dielectric constant of less than about 3.9, the dielectric constant of silicon oxide (SiO2), that is used to insulate adjacent metal lines (interlayer dielectric (ILD) or intermetal dielectric (IMD)) in advanced micro devices. Low-k material reduces capacitive coupling (“cross-talk”) between lines. LK dies are dies with LK IMD (intermetal dielectric) layers, i.e. their IMD layers use LK dielectric materials.
TC is Temperature Cycling and a TC test is conducted to determine the resistance of a part to extremes of high and low temperatures, and to alternate exposures to these extremes. TS is Thermal Shock and the purpose of TS testing is to determine the ability of sold state devices to withstand exposure to extreme changes in temperature by thermally stressing the device. Thermal shock effects include cracking and delamination of substrates or wafers, opening of terminal seals or case seams and changes in electrical characteristics. If more than 30 cycles are performed, the test is considered to be destructive.
Flip-chip packages are not a cost-effective alternative as they cost about 10 times that of HSBGA packages.
U.S. Pat. No. 5,977,633 to Suzuki et al. describes a semiconductor device with metal base substrate having hollows.
U.S. Pat. No. 5,223,741 to Bechtel et al. describes a package for an integrated circuit structure.
U.S. Pat. No. 5,585,671 to Nagesh et al. describes a low thermal resistance package for high power flip chip ICS.
U.S. Pat. No. 6,462,410 B1 to Novotny et al. describes an integrated circuit component temperature gradient reducer.
U.S. Pat. No. 4,748,495 to Kucharek describes a high density multi-chip interconnection and cooling package.